An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures

This paper presents an integrated design system called sparcs (Synthesis and Partitioning for Adaptive Recon gurable Computing Systems) for automatically partitioning and synthesizing designs for recongurable boards with multiple eld-programmable devices (fpgas). The sparcs system accepts design speci cations at the behavior level, in the form of task graphs. The system contains a temporal partitioning tool to temporally divide and schedule the tasks on the recon gurable architecture, a spatial partitioning tool to map the tasks to individual fpgas, and a high-level synthesis tool to synthesize e cient register-transfer level designs for each set of tasks destined to be downloaded on each fpga. Commercial logic and layout synthesis tools are used to complete logic synthesis, placement, and routing for each fpga design segment. A distinguishing feature of the sparcs system is the tight integration of the partitioning and synthesis tools to accurately predict and control design performance and resource utilizations. This paper presents an overview of sparcs and the various algorithms used in the system, along with a brief description of how a jpeg-like image compression algorithm is mapped to a multi-fpga board using sparcs.